The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to lateral SOI devices suitable for high-voltage applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, xe2x80x9conxe2x80x9d resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as xe2x80x9conxe2x80x9d resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One particularly advantageous form of lateral thin-film SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral transistor device in an SOI layer on the buried insulating layer, the device, such as a MOSFET, including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, an at least substantially insulated gate electrode over a channel region of the body region and insulated therefrom, a lateral drift region of the first conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region.
A device of this type is shown in FIG. 1 common to related U.S. Pat. No. 5,246,870 (directed to a method) and U.S. Pat. No. 5,412,241 (directed to a device), commonly-assigned with the instant application and incorporated herein by reference. The device shown in FIG. 1 of the aforementioned patents is a lateral SOI MOSFET device having various features, such as a thinned SOI layer with a linear lateral doping region and an overlying field plate, to enhance operation. As is conventional, this device is an n-channel or NMOS transistor, with n-type source and drain regions, manufactured using a process conventionally referred to as NMOS technology.
More advanced techniques for enhancing high-voltage and high-current performance parameters of SOI power devices are shown in U.S. patent application Ser. No. 08/998,048, of which the present application is a CIP, filed Dec. 24, 1997, commonly-assigned with the instant application and incorporated herein by reference. Yet another technique for improving the performance of an SOI device is to form a hybrid device, which combines more than one type of device configuration into a single structure. Thus, for example, in U.S. patent application Ser. No. 09/122,407, filed Jul. 24, 1998, commonly-assigned with the instant application and incorporated herein by reference, an SOI device is disclosed which includes a lateral DMOS transistor and an LIGB transistor in the same structure.
Thus, it will be apparent that numerous techniques and approaches have been used in order to enhance the performance of power semiconductor devices, in an ongoing effort to attain a more nearly optimum combination of such parameters as breakdown voltage, size, current-carrying capability and manufacturing ease. While all of the foregoing structures provide varying levels of improvement in device performance, no one device or structure fully optimizes all of the design requirements for high-voltage, high-current operation.
Accordingly, it would be desirable to have a transistor device structure capable of high performance in a high-voltage, high-current environment, in which operating parameters, and in particular breakdown voltage, are further optimized.
It is therefore an object of the present invention to provide a transistor device structure capable of high-performance in a high-voltage, high-current environment. It is a further object of the invention to provide such a transistor device structure in which operating parameters such as breakdown voltage are enhanced.
In accordance with the invention, these objects are achieved in a lateral thin-film SOI device structure of the type described above in which a dielectric layer is provided over at least a part of the insulation region and the gate electrode, and a field plate electrode is provided over at least a part of the dielectric layer which is in direct contact with the insulation region, with the field plate electrode being connected to an electrode of the lateral transistor device.
In a preferred embodiment of the invention, the total thickness of the dielectric layer plus the insulation region (i.e. the total xe2x80x9ctopxe2x80x9d insulation thickness) is about equal to the thickness of the buried insulation layer. Typically, the total thickness of the dielectric layer plus the insulation region, and also the thickness of the buried insulation, will each be at least above two microns, and preferably at least about three microns.
In further preferred embodiments of the invention, the gate electrode extends over about one-half of the lateral drift region, and the field plate electrode is connected to either the gate electrode or the source electrode of the lateral transistor device.
Lateral thin-film SOI devices in accordance with the present invention offer a significant improvement in that a combination of favorable performance characteristics making the devices suitable for operation in a high-voltage, high-current environment, and in particular high breakdown voltage, can be achieved.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.